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| author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-25 16:22:50 +0000 |
|---|---|---|
| committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-25 16:22:50 +0000 |
| commit | fc22669ed039ff4e2fc68931d80a672c614e76e0 (patch) | |
| tree | 093410607c73feac180856aba054bedd10cecec5 | |
| parent | 66467166862258718839b86e7c65de399e56d83a (diff) | |
| download | openwrt-fc22669ed039ff4e2fc68931d80a672c614e76e0.tar.gz openwrt-fc22669ed039ff4e2fc68931d80a672c614e76e0.zip | |
AA: ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350
Backport of r34270.
Signed-off-by: Daniel Golle <dgolle@allnet.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@34363 3c298f89-4303-0410-b956-a3cf2f4a3e73
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 2 | ||||
| -rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 949232dbd..943facb6d 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -111,6 +111,8 @@ #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 +#define RT3352_SYSCFG0_XTAL_SEL BIT(20) + #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c index 92ae56d3b..56eae8a9d 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c @@ -215,7 +215,15 @@ static struct platform_device rt305x_wifi_device = { void __init rt305x_register_wifi(void) { + u32 t; rt305x_wifi_data.eeprom_file_name = "RT305X.eeprom"; + + if (soc_is_rt3352() || soc_is_rt5350()) { + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t &= RT3352_SYSCFG0_XTAL_SEL; + if (!t) + rt305x_wifi_data.clk_is_20mhz = 1; + } platform_device_register(&rt305x_wifi_device); } |