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authorRalph Giles <giles@thaumas.net>2015-03-31 11:50:29 +0000
committerRalph Giles <giles@thaumas.net>2015-03-31 11:50:29 +0000
commit910d308998ccab291adfc91d36b33864ea5bed04 (patch)
treee5c12f756570c41d03d7259def94abc325233ad9
parent8acda77289aee8de5c0367fcb79f7599ac9ff5be (diff)
downloadnovena-guide-910d308998ccab291adfc91d36b33864ea5bed04.tar.gz
novena-guide-910d308998ccab291adfc91d36b33864ea5bed04.zip
Fix typo.
It's "it's" for contractions, "its" for possessives
-rw-r--r--fpga-hacking.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga-hacking.rst b/fpga-hacking.rst
index 177b004..34294a6 100644
--- a/fpga-hacking.rst
+++ b/fpga-hacking.rst
@@ -11,7 +11,7 @@ The general purpose FPGA on the Novena mainboard is a Xilinx Spartan6 XC6SLX45
device in the CSG324 BGA package with a ``-3`` speedgrade. It is connected to
the ARM CPU via SPI for bitstream configuration, via i2c for low-speed
communications, and via a 16-bit memory interface ("EIM") for faster
-communications. The FPGA also has it's own DRAM chip and an expansion header to
+communications. The FPGA also has its own DRAM chip and an expansion header to
which extra hardware can be attached.
.. list-table:: Novena FPGA Specifications (from Xilinx)