xilinx.com projects coregen 1.0 fifo_2kx18 fifo_2kx18 Active_High false Empty 2048 false No_Programmable_Full_Threshold false Data_FIFO 18 Full false false false false false false false Common_Clock_Block_RAM Full 1 false false 1024 4 0 false 1 4 Common_Clock_Block_RAM FIFO 1023 1 64 false false 16 1 false No_Programmable_Empty_Threshold 2048 Active_High 4 false false 1022 false Full FIFO Common_Clock_Block_RAM false Full Common_Clock Active_High false false false false Slave_Interface_Clock_Enable 1024 11 1 Common_Clock_Block_RAM Active_High false false 18 false Empty 16 false 2045 Data_FIFO false 11 false false 1022 4 FIFO false false true 1022 Independent_Clocks_Block_RAM Full false 1023 Common_Clock_Block_RAM false Empty 2 false false 1024 false false false Data_FIFO false false false false Empty false 1022 Active_High false FIFO 1 Data_FIFO 1 1022 2044 false false 1023 Native Asynchronous_Reset FIFO 11 false 1023 false Empty false false 64 false Data_FIFO false false Active_High Empty false FIFO false 4 3 Data_FIFO false true Full 1 false 1022 false false Standard_FIFO AXI4_Stream false false Common_Clock_Block_RAM 1023 false true false 32 8 16 1023 false false 0 64 4 5 1023 0 0 32 64 2kx18 0 0 0 11 1023 1 0 0 0 0 4 32 0 18 11 0 1 0 0 1024 0 0 4 0 0 5 1022 1 0 16 0 5 8 0 0 0 0 2 1023 2044 0 1 0 0 1 1 1 1 4 1 0 2048 0 1 1 0 10 1 32 0 1024 1022 1 1 0 0 5 4 16 0 1022 0 2 0 0 0 5 0 0 0 0 64 0 0 0 11 0 0 10 2 5 0 1022 0 11 1 0 1024 4 0 5 0 1022 1023 0 2045 0 0 5 0 0 1 4 2048 0 11 0 5 64 4 0 0 0 0 10 5 1022 1023 1 1 1 1 0 0 5 0 0 3 1023 18 0 0 0 0 0 5 0 1 0 0 0 16 coregen ./ ./tmp/ ./tmp/_cg xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./fifo_2kx18.xco xco Tue Aug 09 21:46:42 GMT 2011 0x200AB8B2 generationid_3501100592 ngc_netlist_generator ./fifo_2kx18.ngc ngc Tue Aug 09 21:47:05 GMT 2011 0x80830D9F generationid_3501100592 ./fifo_2kx18.v verilog Tue Aug 09 21:46:58 GMT 2011 0x6726F87E generationid_3501100592 ./fifo_2kx18.veo veo Tue Aug 09 21:46:58 GMT 2011 0x368CEE5B generationid_3501100592 ./fifo_generator_readme.txt txt Tue Aug 09 21:46:58 GMT 2011 0x8C1691E3 generationid_3501100592 ./fifo_generator_ug175.pdf pdf Tue Aug 09 21:46:58 GMT 2011 0x7B853EF8 generationid_3501100592 instantiation_template_generator ./fifo_2kx18.veo veo Tue Aug 09 21:47:05 GMT 2011 0x368CEE5B generationid_3501100592 asy_generator ./fifo_2kx18.asy asy Tue Aug 09 21:47:08 GMT 2011 0x903A7B6F generationid_3501100592 xmdf_generator ./fifo_2kx18_xmdf.tcl tclXmdf tcl Tue Aug 09 21:47:08 GMT 2011 0xBF5DD5B7 generationid_3501100592 ise_generator ./fifo_2kx18.gise ignore gise Tue Aug 09 21:47:10 GMT 2011 0xAC308EE9 generationid_3501100592 ./fifo_2kx18.xise ignore xise Tue Aug 09 21:47:10 GMT 2011 0xC62EA0FE generationid_3501100592 deliver_readme_generator flist_generator ./fifo_2kx18_flist.txt ignore txtFlist txt Tue Aug 09 21:47:10 GMT 2011 0x64B4445D generationid_3501100592 coregen ./ ./tmp/ ./tmp/_cg xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false