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Chapter Two of "FPGAs!? Now What?" gives a good overview of the full
compilation process:
Synthesis:
the "logic synthesizer" compiles from HDL to a netlist
Implementation:
the "translator" takes a set of netlists and design constraints and generates
a merged netlist (?).
then a "mapper" regroups the netlist so that place and route will be easier
then a "place and route" tool decides exactly how the FPGA logic will be
configured
Bitstream:
the "bitstream generator" translates the configuration into the binary format
that the FPGA uses to re-flash itself
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