From c973b4e327ab0c560ba2428e4cc08d542352eb32 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 2 Apr 2013 10:26:08 -0400 Subject: add old notes and README --- README | 14 +++++++++ notes/.xilinx_filetypes.txt.swp | Bin 0 -> 12288 bytes notes/debugging.txt | 10 +++++++ notes/knowledge.txt | 13 ++++++++ notes/licensing.txt | 8 +++++ notes/style.txt | 7 +++++ notes/tools.txt | 14 +++++++++ notes/unsorted.txt | 21 +++++++++++++ notes/xilinx_filetypes.txt | 65 ++++++++++++++++++++++++++++++++++++++++ notes/xilinx_toolchain.txt | 17 +++++++++++ 10 files changed, 169 insertions(+) create mode 100644 README create mode 100644 notes/.xilinx_filetypes.txt.swp create mode 100644 notes/debugging.txt create mode 100644 notes/knowledge.txt create mode 100644 notes/licensing.txt create mode 100644 notes/style.txt create mode 100644 notes/tools.txt create mode 100644 notes/unsorted.txt create mode 100644 notes/xilinx_filetypes.txt create mode 100644 notes/xilinx_toolchain.txt diff --git a/README b/README new file mode 100644 index 0000000..f18785a --- /dev/null +++ b/README @@ -0,0 +1,14 @@ + + ============================================================= + FPGA LUBE: making programmable logic development less painful + ============================================================= + + +### Repo Contents + +templates/ + +notes/ + tools.txt: list of helpful tools + + diff --git a/notes/.xilinx_filetypes.txt.swp b/notes/.xilinx_filetypes.txt.swp new file mode 100644 index 0000000..2b39a7d Binary files /dev/null and b/notes/.xilinx_filetypes.txt.swp differ diff --git a/notes/debugging.txt b/notes/debugging.txt new file mode 100644 index 0000000..cc1a788 --- /dev/null +++ b/notes/debugging.txt @@ -0,0 +1,10 @@ + + +RED TIN on-chip logic analyser + http://siliconexposed.blogspot.com/2012/06/isim-bugs-and-introducing-red-tin.html + http://code.google.com/p/red-tin-logic-analyzer/ + Use with gtkwave GUI + +sigrok + Soft real-time + diff --git a/notes/knowledge.txt b/notes/knowledge.txt new file mode 100644 index 0000000..bf45730 --- /dev/null +++ b/notes/knowledge.txt @@ -0,0 +1,13 @@ + +Great sources of FPGA knowledge! + +FPGAs!? Now What? + Free/Open FPGA-from-scratch tutorial from XESS. 140+ pages. + Pretty great! + Xilinx WebPack, VHDL, JTAG debug, Spartan. + +MIT 6.111 Labkit Manual + http://www-mtl.mit.edu/Courses/6.111/labkit/ + +WikiBooks: Programmable Logic + http://en.wikibooks.org/wiki/Programmable_Logic diff --git a/notes/licensing.txt b/notes/licensing.txt new file mode 100644 index 0000000..07c2cbd --- /dev/null +++ b/notes/licensing.txt @@ -0,0 +1,8 @@ + +Open Source Semiconductor Core Licensing + by Eli Greenbaum, Harvard Journal of Law and Technology, Fall 2011 + +Xilinx SignOnce IP Licensing + http://www.xilinx.com/products/alliance/signonce.htm + +https://github.com/ewa/free-hdl-license/wiki diff --git a/notes/style.txt b/notes/style.txt new file mode 100644 index 0000000..ddd2ae1 --- /dev/null +++ b/notes/style.txt @@ -0,0 +1,7 @@ + +XXX: verilog style guide here? + +Eg, + +Signed arithmetics in Verilog: The only rule one needs to know +http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/ diff --git a/notes/tools.txt b/notes/tools.txt new file mode 100644 index 0000000..7a0a455 --- /dev/null +++ b/notes/tools.txt @@ -0,0 +1,14 @@ + +QFSM finite state machine tool + http://qfsm.sourceforge.net/about.html + GUI for designing and documenting state machines. looks reasonably mature + generates verilog, vhdl, etc; C, java, ruby code (via ragel); + svg, png diagrams; text, html tables + +doxverilog + http://developer.berlios.de/projects/doxverilog/ + doxygen for verilog + +Minimal Makefile for Xilinx WebPack + http://excamera.com/sphinx/fpga-makefile.html + from gameduino guy diff --git a/notes/unsorted.txt b/notes/unsorted.txt new file mode 100644 index 0000000..65dcf38 --- /dev/null +++ b/notes/unsorted.txt @@ -0,0 +1,21 @@ + +another set of xilinx makefiles + https://github.com/marvin2k/xilinx_makefile + +collection of tools + https://github.com/Ceasar/xilinx_sucks + +scons build scripts for xilinx + https://github.com/ewa/xilinx-build-scripts + +FPGALink JTAG-like thing + http://www.makestuff.eu/wordpress/software/fpgalink/ + +Xillybus + Win/Linux PCI-e DMA IP core and kernel drivers. Proprietary + http://xillybus.com/licensing + +On-chip JTAG for softcores + http://moxielogic.org/blog/?p=704 + from the Moxie processor project + diff --git a/notes/xilinx_filetypes.txt b/notes/xilinx_filetypes.txt new file mode 100644 index 0000000..6639d2f --- /dev/null +++ b/notes/xilinx_filetypes.txt @@ -0,0 +1,65 @@ + +See also: + +https://github.com/JPNaude/X-MimeTypes/blob/master/eda_mime_types.xml +http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgn_r_core_generator_output_files.htm +http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_r_source_types.htm + +also: devref.pdf (UG628) + +Extension Description +--------- -------------------------------------------------------------- +.par "place and route" output +.vhd VHDL source code +.v Verilog source code +.ucf "constraints file": hardware pinouts, timing, etc +.prj [list of files in the project?] +.wcfg [waveform configuration (saved from gtkwave?] +.srp "Synthesis Report File" +.xst [xst settings?] +.lso +.vcf + +.bgn bitgen report file +.bit Final FPGA bitstream file (binary) +.xwbt +.bld Build report from NGDBuild +.blc NGDBuild report file +.cmd_log +.drc Design rule check output +.ncd +.wdb +.exe +.map [intermediate step] +.mrp +.ncd [intermediate step? netlist?] +.ngm +.xrpt +.par [place and route output?] +.pcf +.ptwx +.stx +.syr +.twr +.twx +.unroutes unrouted traces; if routing was successful, there should be none +.ut +.xpi +.log +.xmsgs +.gise +.xise ISE project/workplace + +.cgc [coregen? used to programatically re-gen core?] +.cgp Coregen Project +.ngc Pre-compiled netlist +.sym +.asy "Symbol file" +_flist.txt File list (?) +.gise +.ncf +.sym +.veo +.vho +.xco [intermediate file?] + diff --git a/notes/xilinx_toolchain.txt b/notes/xilinx_toolchain.txt new file mode 100644 index 0000000..e7d78db --- /dev/null +++ b/notes/xilinx_toolchain.txt @@ -0,0 +1,17 @@ + +Chapter Two of "FPGAs!? Now What?" gives a good overview of the full +compilation process: + +Synthesis: + the "logic synthesizer" compiles from HDL to a netlist + +Implementation: + the "translator" takes a set of netlists and design constraints and generates + a merged netlist (?). + then a "mapper" regroups the netlist so that place and route will be easier + then a "place and route" tool decides exactly how the FPGA logic will be + configured + +Bitstream: + the "bitstream generator" translates the configuration into the binary format + that the FPGA uses to re-flash itself -- cgit v1.2.3