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Diffstat (limited to 'docs/xilinx_filetypes_table.txt')
| -rw-r--r-- | docs/xilinx_filetypes_table.txt | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/docs/xilinx_filetypes_table.txt b/docs/xilinx_filetypes_table.txt new file mode 100644 index 0000000..5f68a19 --- /dev/null +++ b/docs/xilinx_filetypes_table.txt @@ -0,0 +1,59 @@ + +=========== ============================================================================== +Extension Description +=========== ============================================================================== +.par "place and route" output +.vhd VHDL source code +.v Verilog source code +.ucf "constraints file": hardware pinouts, timing, etc +.prj [list of files in the project?] +.wcfg [waveform configuration (saved from gtkwave?] +.srp "Synthesis Report File" +.xst [xst settings?] +.lso +.vcf + +.bgn bitgen report file +.bit Final FPGA bitstream file (binary) +.xwbt +.bld Build report from NGDBuild +.blc NGDBuild report file +.cmd_log +.drc Design rule check output +.ncd +.wdb +.exe +.map [intermediate step] +.mrp +.ncd [intermediate step? netlist?] +.ngm +.xrpt +.par [place and route output?] +.pcf +.ptwx +.stx +.syr +.twr +.twx +.unroutes unrouted traces; if routing was successful, there should be none +.ut +.xpi +.log +.xmsgs +.gise +.xise ISE project/workplace + +.cgc [coregen? used to programatically re-gen core?] +.cgp Coregen Project +.ngc Pre-compiled netlist +.sym +.asy "Symbol file" +_flist.txt File list (?) +.gise +.ncf +.sym +.veo +.vho +.xco [intermediate file?] +=========== ============================================================================== + |