pull xilinx notes into sphinx docs

5 files changed, 42 insertions, 27 deletions

diff --git a/docs/index.rst b/docs/index.rst
index 35412a1..d53e14b 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -8,7 +8,9 @@ FPGA LUBE
 Contents:
 
 .. toctree::
-   :maxdepth: 2
+    :maxdepth: 2
+
+    xilinx_toolchain.rst
 
 About This Document
 ---------------------
diff --git a/notes/xilinx_filetypes.txt b/docs/xilinx_filetypes_table.txt
index 6639d2f..5f68a19 100644
--- a/notes/xilinx_filetypes.txt
+++ b/docs/xilinx_filetypes_table.txt
@@ -1,14 +1,7 @@
 
-See also:
-
-https://github.com/JPNaude/X-MimeTypes/blob/master/eda_mime_types.xml
-http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgn_r_core_generator_output_files.htm
-http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_r_source_types.htm
-
-also: devref.pdf (UG628)
-
+=========== ==============================================================================
 Extension   Description
----------   --------------------------------------------------------------
+=========== ==============================================================================
 .par        "place and route" output
 .vhd        VHDL source code
 .v          Verilog source code
@@ -62,4 +55,5 @@ _flist.txt  File list (?)
 .veo
 .vho
 .xco        [intermediate file?]
+=========== ==============================================================================
 
diff --git a/docs/xilinx_toolchain.rst b/docs/xilinx_toolchain.rst
new file mode 100644
index 0000000..ee49621
--- /dev/null
+++ b/docs/xilinx_toolchain.rst
@@ -0,0 +1,36 @@
+
+Xilinx Toolchain
+===================
+
+Chapter Two of "FPGAs!? Now What?" gives a good overview of the full
+compilation process. The basic layers are:
+
+**Synthesis**
+    The "logic synthesizer" compiles from HDL to a netlist
+
+**Implementation**
+    The "translator" takes a set of netlists and design constraints and generates
+    a merged netlist.
+
+    Then a "mapper" regroups the netlist so that place and route will be easier
+
+    Then a "place and route" tool decides exactly how the FPGA logic will be
+    configured
+
+**Bitstream**
+    The "bitstream generator" translates the configuration into the binary
+    format that the FPGA uses to re-flash itself
+
+File Extensions
+-------------------
+
+.. include:: xilinx_filetypes_table.txt
+
+
+See also:
+
+- https://github.com/JPNaude/X-MimeTypes/blob/master/eda_mime_types.xml
+- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgn_r_core_generator_output_files.htm
+- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_r_source_types.htm
+- devref.pdf (UG628)
+
diff --git a/notes/.xilinx_filetypes.txt.swp b/notes/.xilinx_filetypes.txt.swp
deleted file mode 100644
index 2b39a7d..0000000
--- a/notes/.xilinx_filetypes.txt.swp
+++ /dev/null
diff --git a/notes/xilinx_toolchain.txt b/notes/xilinx_toolchain.txt
deleted file mode 100644
index e7d78db..0000000
--- a/notes/xilinx_toolchain.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-
-Chapter Two of "FPGAs!? Now What?" gives a good overview of the full
-compilation process:
-
-Synthesis:
-  the "logic synthesizer" compiles from HDL to a netlist
-
-Implementation:
-  the "translator" takes a set of netlists and design constraints and generates
-      a merged netlist (?).
-  then a "mapper" regroups the netlist so that place and route will be easier
-  then a "place and route" tool decides exactly how the FPGA logic will be
-      configured
-
-Bitstream:
-  the "bitstream generator" translates the configuration into the binary format
-      that the FPGA uses to re-flash itself