From 79ee3c1f847ef472d93c761f0744e3102e707750 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Sat, 3 Nov 2012 08:27:59 +0000 Subject: Split target/Config.in.arch into multiple Config.in.* in arch/ target/Config.in.arch had become too long, and we want to remove the target/ directory. So let's move it to arch/ and split it this way: * An initial Config.in that lists the top-level architecture, and sources the arch-specific Config.in. files, as well as Config.in.common (see below) * One Config.in. per architecture, listing the CPU families, ABI choices, etc. * One Config.in.common that defines the gcc mtune, march, mcpu values and other hidden options. [Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout] Signed-off-by: Thomas Petazzoni Signed-off-by: Peter Korsgaard --- Config.in | 2 +- arch/Config.in | 161 ++++++++++ arch/Config.in.arm | 62 ++++ arch/Config.in.bfin | 10 + arch/Config.in.common | 245 +++++++++++++++ arch/Config.in.mips | 53 ++++ arch/Config.in.powerpc | 83 +++++ arch/Config.in.sh | 24 ++ arch/Config.in.sparc | 38 +++ arch/Config.in.x86 | 146 +++++++++ target/Config.in.arch | 830 ------------------------------------------------- 11 files changed, 823 insertions(+), 831 deletions(-) create mode 100644 arch/Config.in create mode 100644 arch/Config.in.arm create mode 100644 arch/Config.in.bfin create mode 100644 arch/Config.in.common create mode 100644 arch/Config.in.mips create mode 100644 arch/Config.in.powerpc create mode 100644 arch/Config.in.sh create mode 100644 arch/Config.in.sparc create mode 100644 arch/Config.in.x86 delete mode 100644 target/Config.in.arch diff --git a/Config.in b/Config.in index cce4619cd..68190a530 100644 --- a/Config.in +++ b/Config.in @@ -14,7 +14,7 @@ config BR2_HOSTARCH string option env="HOSTARCH" -source "target/Config.in.arch" +source "arch/Config.in" menu "Build options" diff --git a/arch/Config.in b/arch/Config.in new file mode 100644 index 000000000..4d1f81f59 --- /dev/null +++ b/arch/Config.in @@ -0,0 +1,161 @@ +config BR2_ARCH_IS_64 + bool + +choice + prompt "Target Architecture" + default BR2_i386 + help + Select the target architecture family to build for. + +config BR2_arm + bool "ARM (little endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Little endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM + +config BR2_armeb + bool "ARM (big endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Big endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM + +config BR2_aarch64 + bool "AArch64" + help + Aarch64 is a 64-bit architecture developed by ARM Holdings. + http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php + http://en.wikipedia.org/wiki/ARM + +config BR2_avr32 + bool "AVR32" + select BR2_SOFT_FLOAT + help + The AVR32 is a 32-bit RISC microprocessor architecture designed by + Atmel. + http://www.atmel.com/ + http://en.wikipedia.org/wiki/Avr32 + +config BR2_bfin + bool "Blackfin" + help + The Blackfin is a family of 16 or 32-bit microprocessors developed, + manufactured and marketed by Analog Devices. + http://www.analog.com/ + http://en.wikipedia.org/wiki/Blackfin + +config BR2_i386 + bool "i386" + help + Intel i386 architecture compatible microprocessor + http://en.wikipedia.org/wiki/I386 + +config BR2_m68k + bool "m68k" + depends on BROKEN # ice in uclibc / inet_ntoa_r + help + Motorola 68000 family microprocessor + http://en.wikipedia.org/wiki/M68k + +config BR2_microblazeel + bool "Microblaze AXI (little endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus + based architecture (little endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze + +config BR2_microblazebe + bool "Microblaze non-AXI (big endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus + based architecture (non-AXI, big endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze + +config BR2_mips + bool "MIPS (big endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Big endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + +config BR2_mipsel + bool "MIPS (little endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Little endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + +config BR2_mips64 + bool "MIPS64 (big endian)" + select BR2_ARCH_IS_64 + help + MIPS is a RISC microprocessor from MIPS Technologies. Big endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + +config BR2_mips64el + bool "MIPS64 (little endian)" + select BR2_ARCH_IS_64 + help + MIPS is a RISC microprocessor from MIPS Technologies. Little endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + +config BR2_powerpc + bool "PowerPC" + help + PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. + http://www.power.org/ + http://en.wikipedia.org/wiki/Powerpc + +config BR2_sh + bool "SuperH" + help + SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH + +config BR2_sh64 + bool "SuperH64" + help + SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH + +config BR2_sparc + bool "SPARC" + help + SPARC (from Scalable Processor Architecture) is a RISC instruction + set architecture (ISA) developed by Sun Microsystems. + http://www.oracle.com/sun + http://en.wikipedia.org/wiki/Sparc + +config BR2_x86_64 + bool "x86_64" + select BR2_ARCH_IS_64 + help + x86-64 is an extension of the x86 instruction set (Intel i386 + architecture compatible microprocessor). + http://en.wikipedia.org/wiki/X86_64 + +endchoice + +config BR2_microblaze + bool + default y if BR2_microblazeel || BR2_microblazebe + +source "arch/Config.in.arm" +source "arch/Config.in.bfin" +source "arch/Config.in.mips" +source "arch/Config.in.powerpc" +source "arch/Config.in.sh" +source "arch/Config.in.sparc" +source "arch/Config.in.x86" +source "arch/Config.in.common" diff --git a/arch/Config.in.arm b/arch/Config.in.arm new file mode 100644 index 000000000..8d9db3cf0 --- /dev/null +++ b/arch/Config.in.arm @@ -0,0 +1,62 @@ +choice + prompt "Target Architecture Variant" + depends on BR2_arm || BR2_armeb + default BR2_generic_arm + help + Specific CPU variant to use + +config BR2_generic_arm + bool "generic_arm" +config BR2_arm7tdmi + bool "arm7tdmi" +config BR2_arm610 + bool "arm610" +config BR2_arm710 + bool "arm710" +config BR2_arm720t + bool "arm720t" +config BR2_arm920t + bool "arm920t" +config BR2_arm922t + bool "arm922t" +config BR2_arm926t + bool "arm926t" +config BR2_arm10t + bool "arm10t" +config BR2_arm1136jf_s + bool "arm1136jf_s" +config BR2_arm1176jz_s + bool "arm1176jz-s" +config BR2_arm1176jzf_s + bool "arm1176jzf-s" +config BR2_cortex_a8 + bool "cortex-A8" +config BR2_cortex_a9 + bool "cortex-A9" +config BR2_sa110 + bool "sa110" +config BR2_sa1100 + bool "sa1100" +config BR2_xscale + bool "xscale" +config BR2_iwmmxt + bool "iwmmxt" +endchoice + +choice + prompt "Target ABI" + depends on BR2_arm || BR2_armeb + default BR2_ARM_EABI + help + Application Binary Interface to use + + Note: + Using OABI is discouraged. + +config BR2_ARM_EABI + bool "EABI" +config BR2_ARM_OABI + bool "OABI" + depends on !BR2_GCC_VERSION_4_7_X +endchoice + diff --git a/arch/Config.in.bfin b/arch/Config.in.bfin new file mode 100644 index 000000000..1823bde81 --- /dev/null +++ b/arch/Config.in.bfin @@ -0,0 +1,10 @@ +choice + prompt "Target ABI" + depends on BR2_bfin + default BR2_BFIN_FDPIC +config BR2_BFIN_FDPIC + bool "FDPIC" +config BR2_BFIN_FLAT + bool "FLAT" + select BR2_PREFER_STATIC_LIB +endchoice diff --git a/arch/Config.in.common b/arch/Config.in.common new file mode 100644 index 000000000..1ed9929f0 --- /dev/null +++ b/arch/Config.in.common @@ -0,0 +1,245 @@ +config BR2_ARCH + string + default "arm" if BR2_arm + default "armeb" if BR2_armeb + default "aarch64" if BR2_aarch64 + default "avr32" if BR2_avr32 + default "bfin" if BR2_bfin + default "i386" if BR2_x86_i386 + default "i486" if BR2_x86_i486 + default "i586" if BR2_x86_i586 + default "i586" if BR2_x86_pentium_mmx + default "i586" if BR2_x86_geode + default "i586" if BR2_x86_c3 + default "i686" if BR2_x86_c32 + default "i586" if BR2_x86_winchip_c6 + default "i586" if BR2_x86_winchip2 + default "i686" if BR2_x86_i686 + default "i686" if BR2_x86_pentium2 + default "i686" if BR2_x86_pentium3 + default "i686" if BR2_x86_pentium4 + default "i686" if BR2_x86_pentium_m + default "i686" if BR2_x86_pentiumpro + default "i686" if BR2_x86_prescott + default "i686" if BR2_x86_nocona && BR2_i386 + default "i686" if BR2_x86_core2 && BR2_i386 + default "i686" if BR2_x86_atom && BR2_i386 + default "i686" if BR2_x86_opteron && BR2_i386 + default "i686" if BR2_x86_opteron_sse3 && BR2_i386 + default "i686" if BR2_x86_barcelona && BR2_i386 + default "i686" if BR2_x86_k6 + default "i686" if BR2_x86_k6_2 + default "i686" if BR2_x86_athlon + default "i686" if BR2_x86_athlon_4 + default "x86_64" if BR2_x86_64 + default "m68k" if BR2_m68k + default "microblaze" if BR2_microblaze + default "mips" if BR2_mips + default "mipsel" if BR2_mipsel + default "mips64" if BR2_mips64 + default "mips64el" if BR2_mips64el + default "powerpc" if BR2_powerpc + default "sh2" if BR2_sh2 + default "sh2a" if BR2_sh2a + default "sh3" if BR2_sh3 + default "sh3eb" if BR2_sh3eb + default "sh4" if BR2_sh4 + default "sh4eb" if BR2_sh4eb + default "sh4a" if BR2_sh4a + default "sh4aeb" if BR2_sh4aeb + default "sh64" if BR2_sh64 + default "sparc" if BR2_sparc + + +config BR2_ENDIAN + string + default "LITTLE" if BR2_arm || BR2_bfin || BR2_i386 || BR2_mipsel || BR2_mips64el || \ + BR2_sh3 || BR2_sh4 || BR2_sh4a || BR2_x86_64 || BR2_sh64 || \ + BR2_microblazeel + default "BIG" if BR2_armeb || BR2_avr32 || BR2_m68k || BR2_mips || BR2_mips64 || \ + BR2_powerpc || BR2_sh2 || BR2_sh2a || \ + BR2_sh3eb || BR2_sh4eb || BR2_sh4aeb || BR2_sparc || \ + BR2_microblazebe + +config BR2_GCC_TARGET_TUNE + string + default i386 if BR2_x86_i386 + default i486 if BR2_x86_i486 + default i586 if BR2_x86_i586 + default pentium-mmx if BR2_x86_pentium_mmx + default i686 if BR2_x86_i686 + default pentiumpro if BR2_x86_pentiumpro + default pentium-m if BR2_x86_pentium_m + default pentium2 if BR2_x86_pentium2 + default pentium3 if BR2_x86_pentium3 + default pentium4 if BR2_x86_pentium4 + default prescott if BR2_x86_prescott + default nocona if BR2_x86_nocona + default core2 if BR2_x86_core2 + default atom if BR2_x86_atom + default k8 if BR2_x86_opteron + default k8-sse3 if BR2_x86_opteron_sse3 + default barcelona if BR2_x86_barcelona + default k6 if BR2_x86_k6 + default k6-2 if BR2_x86_k6_2 + default athlon if BR2_x86_athlon + default athlon-4 if BR2_x86_athlon_4 + default winchip-c6 if BR2_x86_winchip_c6 + default winchip2 if BR2_x86_winchip2 + default c3 if BR2_x86_c3 + default c3-2 if BR2_x86_c32 + default geode if BR2_x86_geode + default generic if BR2_x86_generic + default arm600 if BR2_arm600 + default arm610 if BR2_arm610 + default arm620 if BR2_arm620 + default arm7tdmi if BR2_arm7tdmi + default arm7tdmi if BR2_arm720t + default arm7tdmi if BR2_arm740t + default arm920 if BR2_arm920 + default arm920t if BR2_arm920t + default arm922t if BR2_arm922t + default arm926ej-s if BR2_arm926t + default arm1136j-s if BR2_arm1136j_s + default arm1136jf-s if BR2_arm1136jf_s + default arm1176jz-s if BR2_arm1176jz_s + default arm1176jzf-s if BR2_arm1176jzf_s + default cortex-a8 if BR2_cortex_a8 + default cortex-a9 if BR2_cortex_a9 + default strongarm110 if BR2_sa110 + default strongarm1100 if BR2_sa1100 + default xscale if BR2_xscale + default iwmmxt if BR2_iwmmxt + default 68000 if BR2_m68k_68000 + default 68010 if BR2_m68k_68010 + default 68020 if BR2_m68k_68020 + default 68030 if BR2_m68k_68030 + default 68040 if BR2_m68k_68040 + default 68060 if BR2_m68k_68060 + default mips1 if BR2_mips_1 + default mips2 if BR2_mips_2 + default mips3 if BR2_mips_3 + default mips4 if BR2_mips_4 + default mips32 if BR2_mips_32 + default mips32r2 if BR2_mips_32r2 + default mips64 if BR2_mips_64 + default mips64r2 if BR2_mips_64r2 + default 401 if BR2_powerpc_401 + default 403 if BR2_powerpc_403 + default 405 if BR2_powerpc_405 + default 405fp if BR2_powerpc_405fp + default 440 if BR2_powerpc_440 + default 440fp if BR2_powerpc_440fp + default 505 if BR2_powerpc_505 + default 601 if BR2_powerpc_601 + default 602 if BR2_powerpc_602 + default 603 if BR2_powerpc_603 + default 603e if BR2_powerpc_603e + default 604 if BR2_powerpc_604 + default 604e if BR2_powerpc_604e + default 620 if BR2_powerpc_620 + default 630 if BR2_powerpc_630 + default 740 if BR2_powerpc_740 + default 7400 if BR2_powerpc_7400 + default 7450 if BR2_powerpc_7450 + default 750 if BR2_powerpc_750 + default 801 if BR2_powerpc_801 + default 821 if BR2_powerpc_821 + default 823 if BR2_powerpc_823 + default 860 if BR2_powerpc_860 + default 970 if BR2_powerpc_970 + default 8540 if BR2_powerpc_8540 + default 8548 if BR2_powerpc_8548 + default e300c2 if BR2_powerpc_e300c2 + default e300c3 if BR2_powerpc_e300c3 + default e500mc if BR2_powerpc_e500mc + default v7 if BR2_sparc_v7 + default cypress if BR2_sparc_cypress + default v8 if BR2_sparc_v8 + default supersparc if BR2_sparc_supersparc + default hypersparc if BR2_sparc_hypersparc + default sparclite if BR2_sparc_sparclite + default f930 if BR2_sparc_f930 + default f934 if BR2_sparc_f934 + default sparclite86x if BR2_sparc_sparclite86x + default sparclet if BR2_sparc_sparclet + default tsc701 if BR2_sparc_tsc701 + default v9 if BR2_sparc_v9 + default v9 if BR2_sparc_v9a + default v9 if BR2_sparc_v9b + default ultrasparc if BR2_sparc_ultrasparc + default ultrasparc3 if BR2_sparc_ultrasparc3 + default niagara if BR2_sparc_niagara + +config BR2_GCC_TARGET_ARCH + string + default i386 if BR2_x86_i386 + default i486 if BR2_x86_i486 + default i586 if BR2_x86_i586 + default pentium-mmx if BR2_x86_pentium_mmx + default i686 if BR2_x86_i686 + default pentiumpro if BR2_x86_pentiumpro + default pentium-m if BR2_x86_pentium_m + default pentium2 if BR2_x86_pentium2 + default pentium3 if BR2_x86_pentium3 + default pentium4 if BR2_x86_pentium4 + default prescott if BR2_x86_prescott + default nocona if BR2_x86_nocona + default core2 if BR2_x86_core2 + default atom if BR2_x86_atom + default k8 if BR2_x86_opteron + default k8-sse3 if BR2_x86_opteron_sse3 + default barcelona if BR2_x86_barcelona + default k6 if BR2_x86_k6 + default k6-2 if BR2_x86_k6_2 + default athlon if BR2_x86_athlon + default athlon-4 if BR2_x86_athlon_4 + default winchip-c6 if BR2_x86_winchip_c6 + default winchip2 if BR2_x86_winchip2 + default c3 if BR2_x86_c3 + default c3-2 if BR2_x86_c32 + default geode if BR2_x86_geode + default armv4t if BR2_arm7tdmi + default armv3 if BR2_arm610 + default armv3 if BR2_arm710 + default armv4t if BR2_arm720t + default armv4t if BR2_arm920t + default armv4t if BR2_arm922t + default armv5te if BR2_arm926t + default armv5t if BR2_arm10t + default armv6j if BR2_arm1136jf_s + default armv6zk if BR2_arm1176jz_s + default armv6zk if BR2_arm1176jzf_s + default armv7-a if BR2_cortex_a8 + default armv7-a if BR2_cortex_a9 + default armv4 if BR2_sa110 + default armv4 if BR2_sa1100 + default armv5te if BR2_xscale + default iwmmxt if BR2_iwmmxt + default 68000 if BR2_m68k_68000 + default 68010 if BR2_m68k_68010 + default 68020 if BR2_m68k_68020 + default 68030 if BR2_m68k_68030 + default 68040 if BR2_m68k_68040 + default 68060 if BR2_m68k_68060 + +config BR2_GCC_TARGET_ABI + string + default apcs-gnu if BR2_ARM_OABI + default aapcs-linux if BR2_ARM_EABI + default 32 if BR2_MIPS_OABI32 + default n32 if BR2_MIPS_NABI32 + default 64 if BR2_MIPS_NABI64 + default altivec if BR2_powerpc && BR2_PPC_ABI_altivec + default no-altivec if BR2_powerpc && BR2_PPC_ABI_no-altivec + default spe if BR2_powerpc && BR2_PPC_ABI_spe + default no-spe if BR2_powerpc && BR2_PPC_ABI_no-spe + default ibmlongdouble if BR2_powerpc && BR2_PPC_ABI_ibmlongdouble + default ieeelongdouble if BR2_powerpc && BR2_PPC_ABI_ieeelongdouble + +config BR2_GCC_TARGET_CPU + string + default sparchfleon if BR2_sparc_sparchfleon + default sparchfleonv8 if BR2_sparc_sparchfleonv8 + default sparcsfleon if BR2_sparc_sparcsfleon + default sparcsfleonv8 if BR2_sparc_sparcsfleonv8 diff --git a/arch/Config.in.mips b/arch/Config.in.mips new file mode 100644 index 000000000..93a21bfae --- /dev/null +++ b/arch/Config.in.mips @@ -0,0 +1,53 @@ +choice + prompt "Target Architecture Variant" + depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el + default BR2_mips_3 if BR2_mips + default BR2_mips_1 if BR2_mipsel + default BR2_mips_64 if BR2_mips64 || BR2_mips64el + help + Specific CPU variant to use + + 64bit cabable: 3, 4, 64, 64r2 + non-64bit capable: 1, 2, 32, 32r2 + +config BR2_mips_1 + bool "mips I (generic)" + depends on !BR2_ARCH_IS_64 +config BR2_mips_2 + bool "mips II" + depends on !BR2_ARCH_IS_64 +config BR2_mips_3 + bool "mips III" +config BR2_mips_4 + bool "mips IV" +config BR2_mips_32 + bool "mips 32" + depends on !BR2_ARCH_IS_64 +config BR2_mips_32r2 + bool "mips 32r2" + depends on !BR2_ARCH_IS_64 +config BR2_mips_64 + bool "mips 64" +config BR2_mips_64r2 + bool "mips 64r2" +endchoice + + +choice + prompt "Target ABI" + depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el + default BR2_MIPS_OABI32 if !BR2_ARCH_IS_64 + default BR2_MIPS_NABI32 if BR2_ARCH_IS_64 + + help + Application Binary Interface to use + +config BR2_MIPS_OABI32 + bool "o32" +config BR2_MIPS_NABI32 + bool "n32" + depends on BR2_ARCH_IS_64 +config BR2_MIPS_NABI64 + bool "n64" + depends on BR2_ARCH_IS_64 +endchoice diff --git a/arch/Config.in.powerpc b/arch/Config.in.powerpc new file mode 100644 index 000000000..20b0b064d --- /dev/null +++ b/arch/Config.in.powerpc @@ -0,0 +1,83 @@ +choice + prompt "Target Architecture Variant" + depends on BR2_powerpc + default BR2_generic_powerpc + help + Specific CPU variant to use +config BR2_generic_powerpc + bool "generic" +config BR2_powerpc_401 + bool "401" +config BR2_powerpc_403 + bool "403" +config BR2_powerpc_405 + bool "405" +config BR2_powerpc_405fp + bool "405 with FPU" +config BR2_powerpc_440 + bool "440" +config BR2_powerpc_440fp + bool "440 with FPU" +config BR2_powerpc_505 + bool "505" +config BR2_powerpc_601 + bool "601" +config BR2_powerpc_602 + bool "602" +config BR2_powerpc_603 + bool "603" +config BR2_powerpc_603e + bool "603e" +config BR2_powerpc_604 + bool "604" +config BR2_powerpc_604e + bool "604e" +config BR2_powerpc_620 + bool "620" +config BR2_powerpc_630 + bool "630" +config BR2_powerpc_740 + bool "740" +config BR2_powerpc_7400 + bool "7400" +config BR2_powerpc_7450 + bool "7450" +config BR2_powerpc_750 + bool "750" +config BR2_powerpc_801 + bool "801" +config BR2_powerpc_821 + bool "821" +config BR2_powerpc_823 + bool "823" +config BR2_powerpc_860 + bool "860" +config BR2_powerpc_970 + bool "970" +config BR2_powerpc_8540 + bool "8540 / e500v1" +config BR2_powerpc_8548 + bool "8548 / e500v2" +config BR2_powerpc_e300c2 + bool "e300c2" +config BR2_powerpc_e300c3 + bool "e300c3" +config BR2_powerpc_e500mc + bool "e500mc" +endchoice + +choice + prompt "Target ABI" + depends on BR2_powerpc + default BR2_powerpc_SPE if BR2_powerpc_8540 || BR2_powerpc_8548 + default BR2_powerpc_CLASSIC + help + Application Binary Interface to use + +config BR2_powerpc_CLASSIC + bool "Classic" + depends on !(BR2_powerpc_8540 || BR2_powerpc_8548) +config BR2_powerpc_SPE + bool "SPE" + depends on BR2_powerpc_8540 || BR2_powerpc_8548 +endchoice diff --git a/arch/Config.in.sh b/arch/Config.in.sh new file mode 100644 index 000000000..314c55ae9 --- /dev/null +++ b/arch/Config.in.sh @@ -0,0 +1,24 @@ +choice + prompt "Target Architecture Variant" + depends on BR2_sh + default BR2_sh4 + help + Specific CPU variant to use + +config BR2_sh2 + bool "sh2 (SH2 big endian)" +config BR2_sh2a + bool "sh2a (SH2A big endian)" +config BR2_sh3 + bool "sh3 (SH3 little endian)" +config BR2_sh3eb + bool "sh3eb (SH3 big endian)" +config BR2_sh4 + bool "sh4 (SH4 little endian)" +config BR2_sh4eb + bool "sh4eb (SH4 big endian)" +config BR2_sh4a + bool "sh4a (SH4A little endian)" +config BR2_sh4aeb + bool "sh4aeb (SH4A big endian)" +endchoice diff --git a/arch/Config.in.sparc b/arch/Config.in.sparc new file mode 100644 index 000000000..85e0833a0 --- /dev/null +++ b/arch/Config.in.sparc @@ -0,0 +1,38 @@ +choice + prompt "Target Architecture Variant" + depends on BR2_sparc + default BR2_sparc_v7 + help + Specific CPU variant to use + +config BR2_sparc_v7 + bool "v7" +config BR2_sparc_cypress + bool "cypress" +config BR2_sparc_v8 + bool "v8" +config BR2_sparc_sparchfleon + bool "hfleon" +config BR2_sparc_sparchfleonv8 + bool "hfleonv8" +config BR2_sparc_sparcsfleon + bool "sfleon" +config BR2_sparc_sparcsfleonv8 + bool "sfleonv8" +config BR2_sparc_supersparc + bool "supersparc" +config BR2_sparc_sparclite + bool "sparclite" +config BR2_sparc_f930 + bool "f930" +config BR2_sparc_f934 + bool "f934" +config BR2_sparc_hypersparc + bool "hypersparc" +config BR2_sparc_sparclite86x + bool "sparclite86x" +config BR2_sparc_sparclet + bool "sparclet" +config BR2_sparc_tsc701 + bool "tsc701" +endchoice diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 new file mode 100644 index 000000000..4f32d7458 --- /dev/null +++ b/arch/Config.in.x86 @@ -0,0 +1,146 @@ +# i386/x86_64 cpu features +config BR2_X86_CPU_HAS_MMX + bool +config BR2_X86_CPU_HAS_SSE + bool +config BR2_X86_CPU_HAS_SSE2 + bool +config BR2_X86_CPU_HAS_SSE3 + bool +config BR2_X86_CPU_HAS_SSSE3 + bool + +choice + prompt "Target Architecture Variant" + depends on BR2_i386 || BR2_x86_64 + default BR2_x86_i586 if BR2_i386 + default BR2_x86_generic if BR2_x86_64 + help + Specific CPU variant to use + +config BR2_x86_generic + bool "generic" +config BR2_x86_i386 + bool "i386" + depends on !BR2_x86_64 +config BR2_x86_i486 + bool "i486" + depends on !BR2_x86_64 +config BR2_x86_i586 + bool "i586" + depends on !BR2_x86_64 +config BR2_x86_i686 + bool "i686" + depends on !BR2_x86_64 +config BR2_x86_pentiumpro + bool "pentium pro" + depends on !BR2_x86_64 +config BR2_x86_pentium_mmx + bool "pentium MMX" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_pentium_m + bool "pentium mobile" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_pentium2 + bool "pentium2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_pentium3 + bool "pentium3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_pentium4 + bool "pentium4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + depends on !BR2_x86_64 +config BR2_x86_prescott + bool "prescott" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + depends on !BR2_x86_64 +config BR2_x86_nocona + bool "nocona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_core2 + bool "core2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 +config BR2_x86_atom + bool "atom" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 +config BR2_x86_k6 + bool "k6" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_k6_2 + bool "k6-2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_athlon + bool "athlon" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_athlon_4 + bool "athlon-4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_opteron + bool "opteron" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 +config BR2_x86_opteron_sse3 + bool "opteron w/ SSE3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_barcelona + bool "barcelona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_geode + bool "geode" + # Don't include MMX support because there several variant of geode + # processor, some with MMX support, some without. + # See: http://en.wikipedia.org/wiki/Geode_%28processor%29 + depends on !BR2_x86_64 +config BR2_x86_c3 + bool "Via/Cyrix C3 (Samuel/Ezra cores)" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_c32 + bool "Via C3-2 (Nehemiah cores)" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_winchip_c6 + bool "IDT Winchip C6" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_winchip2 + bool "IDT Winchip 2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +endchoice diff --git a/target/Config.in.arch b/target/Config.in.arch deleted file mode 100644 index ac2c0b599..000000000 --- a/target/Config.in.arch +++ /dev/null @@ -1,830 +0,0 @@ -config BR2_ARCH_IS_64 - bool - -choice - prompt "Target Architecture" - default BR2_i386 - help - Select the target architecture family to build for. - -config BR2_arm - bool "ARM (little endian)" - help - ARM is a 32-bit reduced instruction set computer (RISC) instruction - set architecture (ISA) developed by ARM Holdings. Little endian. - http://www.arm.com/ - http://en.wikipedia.org/wiki/ARM - -config BR2_armeb - bool "ARM (big endian)" - help - ARM is a 32-bit reduced instruction set computer (RISC) instruction - set architecture (ISA) developed by ARM Holdings. Big endian. - http://www.arm.com/ - http://en.wikipedia.org/wiki/ARM - -config BR2_aarch64 - bool "AArch64" - help - Aarch64 is a 64-bit architecture developed by ARM Holdings. - http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php - http://en.wikipedia.org/wiki/ARM - -config BR2_avr32 - bool "AVR32" - select BR2_SOFT_FLOAT - help - The AVR32 is a 32-bit RISC microprocessor architecture designed by - Atmel. - http://www.atmel.com/ - http://en.wikipedia.org/wiki/Avr32 - -config BR2_bfin - bool "Blackfin" - help - The Blackfin is a family of 16 or 32-bit microprocessors developed, - manufactured and marketed by Analog Devices. - http://www.analog.com/ - http://en.wikipedia.org/wiki/Blackfin - -config BR2_i386 - bool "i386" - help - Intel i386 architecture compatible microprocessor - http://en.wikipedia.org/wiki/I386 - -config BR2_m68k - bool "m68k" - depends on BROKEN # ice in uclibc / inet_ntoa_r - help - Motorola 68000 family microprocessor - http://en.wikipedia.org/wiki/M68k - -config BR2_microblazeel - bool "Microblaze AXI (little endian)" - help - Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus - based architecture (little endian) - http://www.xilinx.com - http://en.wikipedia.org/wiki/Microblaze - -config BR2_microblazebe - bool "Microblaze non-AXI (big endian)" - help - Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus - based architecture (non-AXI, big endian) - http://www.xilinx.com - http://en.wikipedia.org/wiki/Microblaze - -config BR2_mips - bool "MIPS (big endian)" - help - MIPS is a RISC microprocessor from MIPS Technologies. Big endian. - http://www.mips.com/ - http://en.wikipedia.org/wiki/MIPS_Technologies - -config BR2_mipsel - bool "MIPS (little endian)" - help - MIPS is a RISC microprocessor from MIPS Technologies. Little endian. - http://www.mips.com/ - http://en.wikipedia.org/wiki/MIPS_Technologies - -config BR2_mips64 - bool "MIPS64 (big endian)" - select BR2_ARCH_IS_64 - help - MIPS is a RISC microprocessor from MIPS Technologies. Big endian. - http://www.mips.com/ - http://en.wikipedia.org/wiki/MIPS_Technologies - -config BR2_mips64el - bool "MIPS64 (little endian)" - select BR2_ARCH_IS_64 - help - MIPS is a RISC microprocessor from MIPS Technologies. Big endian. - http://www.mips.com/ - http://en.wikipedia.org/wiki/MIPS_Technologies - -config BR2_powerpc - bool "PowerPC" - help - PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. - http://www.power.org/ - http://en.wikipedia.org/wiki/Powerpc - -config BR2_sh - bool "SuperH" - help - SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) - instruction set architecture (ISA) developed by Hitachi. - http://www.hitachi.com/ - http://en.wikipedia.org/wiki/SuperH - -config BR2_sh64 - bool "SuperH64" - help - SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC) - instruction set architecture (ISA) developed by Hitachi. - http://www.hitachi.com/ - http://en.wikipedia.org/wiki/SuperH - -config BR2_sparc - bool "SPARC" - help - SPARC (from Scalable Processor Architecture) is a RISC instruction - set architecture (ISA) developed by Sun Microsystems. - http://www.oracle.com/sun - http://en.wikipedia.org/wiki/Sparc - -config BR2_x86_64 - bool "x86_64" - select BR2_ARCH_IS_64 - help - x86-64 is an extension of the x86 instruction set (Intel i386 - architecture compatible microprocessor). - http://en.wikipedia.org/wiki/X86_64 - -endchoice - -config BR2_microblaze - bool - default y if BR2_microblazeel || BR2_microblazebe - -# -# Keep the variants separate, there's no need to clutter everything else. -# sh is fairly "special" in this regard, as virtually everyone else has -# things kept down to a _sensible_ number of target variants. No such -# luck for sh.. -# -choice - prompt "Target Architecture Variant" - depends on BR2_arm || BR2_armeb - default BR2_generic_arm - help - Specific CPU variant to use - -config BR2_generic_arm - bool "generic_arm" -config BR2_arm7tdmi - bool "arm7tdmi" -config BR2_arm610 - bool "arm610" -config BR2_arm710 - bool "arm710" -config BR2_arm720t - bool "arm720t" -config BR2_arm920t - bool "arm920t" -config BR2_arm922t - bool "arm922t" -config BR2_arm926t - bool "arm926t" -config BR2_arm10t - bool "arm10t" -config BR2_arm1136jf_s - bool "arm1136jf_s" -config BR2_arm1176jz_s - bool "arm1176jz-s" -config BR2_arm1176jzf_s - bool "arm1176jzf-s" -config BR2_cortex_a8 - bool "cortex-A8" -config BR2_cortex_a9 - bool "cortex-A9" -config BR2_sa110 - bool "sa110" -config BR2_sa1100 - bool "sa1100" -config BR2_xscale - bool "xscale" -config BR2_iwmmxt - bool "iwmmxt" -endchoice - -choice - prompt "Target ABI" - depends on BR2_arm || BR2_armeb - default BR2_ARM_EABI - help - Application Binary Interface to use - - Note: - Using OABI is discouraged. - -config BR2_ARM_EABI - bool "EABI" -config BR2_ARM_OABI - bool "OABI" - depends on !BR2_GCC_VERSION_4_7_X -endchoice - -choice - prompt "Target ABI" - depends on BR2_bfin - default BR2_BFIN_FDPIC -config BR2_BFIN_FDPIC - bool "FDPIC" -config BR2_BFIN_FLAT - bool "FLAT" - select BR2_PREFER_STATIC_LIB -endchoice - -choice - prompt "Target Architecture Variant" - depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el - default BR2_mips_3 if BR2_mips - default BR2_mips_1 if BR2_mipsel - default BR2_mips_64 if BR2_mips64 || BR2_mips64el - help - Specific CPU variant to use - - 64bit cabable: 3, 4, 64, 64r2 - non-64bit capable: 1, 2, 32, 32r2 - -config BR2_mips_1 - bool "mips I (generic)" - depends on !BR2_ARCH_IS_64 -config BR2_mips_2 - bool "mips II" - depends on !BR2_ARCH_IS_64 -config BR2_mips_3 - bool "mips III" -config BR2_mips_4 - bool "mips IV" -config BR2_mips_32 - bool "mips 32" - depends on !BR2_ARCH_IS_64 -config BR2_mips_32r2 - bool "mips 32r2" - depends on !BR2_ARCH_IS_64 -config BR2_mips_64 - bool "mips 64" -config BR2_mips_64r2 - bool "mips 64r2" -endchoice - - -choice - prompt "Target ABI" - depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el - default BR2_MIPS_OABI32 if !BR2_ARCH_IS_64 - default BR2_MIPS_NABI32 if BR2_ARCH_IS_64 - help - Application Binary Interface to use - -config BR2_MIPS_OABI32 - bool "o32" -config BR2_MIPS_NABI32 - bool "n32" - depends on BR2_ARCH_IS_64 -config BR2_MIPS_NABI64 - bool "n64" - depends on BR2_ARCH_IS_64 -endchoice - -choice - prompt "Target Architecture Variant" - depends on BR2_sh - default BR2_sh4 - help - Specific CPU variant to use - -config BR2_sh2 - bool "sh2 (SH2 big endian)" -config BR2_sh2a - bool "sh2a (SH2A big endian)" -config BR2_sh3 - bool "sh3 (SH3 little endian)" -config BR2_sh3eb - bool "sh3eb (SH3 big endian)" -config BR2_sh4 - bool "sh4 (SH4 little endian)" -config BR2_sh4eb - bool "sh4eb (SH4 big endian)" -config BR2_sh4a - bool "sh4a (SH4A little endian)" -config BR2_sh4aeb - bool "sh4aeb (SH4A big endian)" -endchoice - -# -# gcc builds libstdc++ differently depending on the -# host tuplet given to it, so let people choose -# - -# i386/x86_64 cpu features -config BR2_X86_CPU_HAS_MMX - bool -config BR2_X86_CPU_HAS_SSE - bool -config BR2_X86_CPU_HAS_SSE2 - bool -config BR2_X86_CPU_HAS_SSE3 - bool -config BR2_X86_CPU_HAS_SSSE3 - bool - -choice - prompt "Target Architecture Variant" - depends on BR2_i386 || BR2_x86_64 - default BR2_x86_i586 if BR2_i386 - default BR2_x86_generic if BR2_x86_64 - help - Specific CPU variant to use - -config BR2_x86_generic - bool "generic" -config BR2_x86_i386 - bool "i386" - depends on !BR2_x86_64 -config BR2_x86_i486 - bool "i486" - depends on !BR2_x86_64 -config BR2_x86_i586 - bool "i586" - depends on !BR2_x86_64 -config BR2_x86_i686 - bool "i686" - depends on !BR2_x86_64 -config BR2_x86_pentiumpro - bool "pentium pro" - depends on !BR2_x86_64 -config BR2_x86_pentium_mmx - bool "pentium MMX" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_pentium_m - bool "pentium mobile" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - depends on !BR2_x86_64 -config BR2_x86_pentium2 - bool "pentium2" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_pentium3 - bool "pentium3" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - depends on !BR2_x86_64 -config BR2_x86_pentium4 - bool "pentium4" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - depends on !BR2_x86_64 -config BR2_x86_prescott - bool "prescott" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 - depends on !BR2_x86_64 -config BR2_x86_nocona - bool "nocona" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 -config BR2_x86_core2 - bool "core2" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 - select BR2_X86_CPU_HAS_SSSE3 -config BR2_x86_atom - bool "atom" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 - select BR2_X86_CPU_HAS_SSSE3 -config BR2_x86_k6 - bool "k6" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_k6_2 - bool "k6-2" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_athlon - bool "athlon" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_athlon_4 - bool "athlon-4" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - depends on !BR2_x86_64 -config BR2_x86_opteron - bool "opteron" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 -config BR2_x86_opteron_sse3 - bool "opteron w/ SSE3" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 -config BR2_x86_barcelona - bool "barcelona" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - select BR2_X86_CPU_HAS_SSE2 - select BR2_X86_CPU_HAS_SSE3 -config BR2_x86_geode - bool "geode" - # Don't include MMX support because there several variant of geode - # processor, some with MMX support, some without. - # See: http://en.wikipedia.org/wiki/Geode_%28processor%29 - depends on !BR2_x86_64 -config BR2_x86_c3 - bool "Via/Cyrix C3 (Samuel/Ezra cores)" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_c32 - bool "Via C3-2 (Nehemiah cores)" - select BR2_X86_CPU_HAS_MMX - select BR2_X86_CPU_HAS_SSE - depends on !BR2_x86_64 -config BR2_x86_winchip_c6 - bool "IDT Winchip C6" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -config BR2_x86_winchip2 - bool "IDT Winchip 2" - select BR2_X86_CPU_HAS_MMX - depends on !BR2_x86_64 -endchoice - -choice - prompt "Target Architecture Variant" - depends on BR2_sparc - default BR2_sparc_v7 - help - Specific CPU variant to use - -config BR2_sparc_v7 - bool "v7" -config BR2_sparc_cypress - bool "cypress" -config BR2_sparc_v8 - bool "v8" -config BR2_sparc_sparchfleon - bool "hfleon" -config BR2_sparc_sparchfleonv8 - bool "hfleonv8" -config BR2_sparc_sparcsfleon - bool "sfleon" -config BR2_sparc_sparcsfleonv8 - bool "sfleonv8" -config BR2_sparc_supersparc - bool "supersparc" -config BR2_sparc_sparclite - bool "sparclite" -config BR2_sparc_f930 - bool "f930" -config BR2_sparc_f934 - bool "f934" -config BR2_sparc_hypersparc - bool "hypersparc" -config BR2_sparc_sparclite86x - bool "sparclite86x" -config BR2_sparc_sparclet - bool "sparclet" -config BR2_sparc_tsc701 - bool "tsc701" -endchoice - -choice - prompt "Target Architecture Variant" - depends on BR2_powerpc - default BR2_generic_powerpc - help - Specific CPU variant to use -config BR2_generic_powerpc - bool "generic" -config BR2_powerpc_401 - bool "401" -config BR2_powerpc_403 - bool "403" -config BR2_powerpc_405 - bool "405" -config BR2_powerpc_405fp - bool "405 with FPU" -config BR2_powerpc_440 - bool "440" -config BR2_powerpc_440fp - bool "440 with FPU" -config BR2_powerpc_505 - bool "505" -config BR2_powerpc_601 - bool "601" -config BR2_powerpc_602 - bool "602" -config BR2_powerpc_603 - bool "603" -config BR2_powerpc_603e - bool "603e" -config BR2_powerpc_604 - bool "604" -config BR2_powerpc_604e - bool "604e" -config BR2_powerpc_620 - bool "620" -config BR2_powerpc_630 - bool "630" -config BR2_powerpc_740 - bool "740" -config BR2_powerpc_7400 - bool "7400" -config BR2_powerpc_7450 - bool "7450" -config BR2_powerpc_750 - bool "750" -config BR2_powerpc_801 - bool "801" -config BR2_powerpc_821 - bool "821" -config BR2_powerpc_823 - bool "823" -config BR2_powerpc_860 - bool "860" -config BR2_powerpc_970 - bool "970" -config BR2_powerpc_8540 - bool "8540 / e500v1" -config BR2_powerpc_8548 - bool "8548 / e500v2" -config BR2_powerpc_e300c2 - bool "e300c2" -config BR2_powerpc_e300c3 - bool "e300c3" -config BR2_powerpc_e500mc - bool "e500mc" -endchoice - -choice - prompt "Target ABI" - depends on BR2_powerpc - default BR2_powerpc_SPE if BR2_powerpc_8540 || BR2_powerpc_8548 - default BR2_powerpc_CLASSIC - help - Application Binary Interface to use - -config BR2_powerpc_CLASSIC - bool "Classic" - depends on !(BR2_powerpc_8540 || BR2_powerpc_8548) -config BR2_powerpc_SPE - bool "SPE" - depends on BR2_powerpc_8540 || BR2_powerpc_8548 -endchoice - -config BR2_ARCH - string - default "arm" if BR2_arm - default "armeb" if BR2_armeb - default "aarch64" if BR2_aarch64 - default "avr32" if BR2_avr32 - default "bfin" if BR2_bfin - default "i386" if BR2_x86_i386 - default "i486" if BR2_x86_i486 - default "i586" if BR2_x86_i586 - default "i586" if BR2_x86_pentium_mmx - default "i586" if BR2_x86_geode - default "i586" if BR2_x86_c3 - default "i686" if BR2_x86_c32 - default "i586" if BR2_x86_winchip_c6 - default "i586" if BR2_x86_winchip2 - default "i686" if BR2_x86_i686 - default "i686" if BR2_x86_pentium2 - default "i686" if BR2_x86_pentium3 - default "i686" if BR2_x86_pentium4 - default "i686" if BR2_x86_pentium_m - default "i686" if BR2_x86_pentiumpro - default "i686" if BR2_x86_prescott - default "i686" if BR2_x86_nocona && BR2_i386 - default "i686" if BR2_x86_core2 && BR2_i386 - default "i686" if BR2_x86_atom && BR2_i386 - default "i686" if BR2_x86_opteron && BR2_i386 - default "i686" if BR2_x86_opteron_sse3 && BR2_i386 - default "i686" if BR2_x86_barcelona && BR2_i386 - default "i686" if BR2_x86_k6 - default "i686" if BR2_x86_k6_2 - default "i686" if BR2_x86_athlon - default "i686" if BR2_x86_athlon_4 - default "x86_64" if BR2_x86_64 - default "m68k" if BR2_m68k - default "microblaze" if BR2_microblaze - default "mips" if BR2_mips - default "mipsel" if BR2_mipsel - default "mips64" if BR2_mips64 - default "mips64el" if BR2_mips64el - default "powerpc" if BR2_powerpc - default "sh2" if BR2_sh2 - default "sh2a" if BR2_sh2a - default "sh3" if BR2_sh3 - default "sh3eb" if BR2_sh3eb - default "sh4" if BR2_sh4 - default "sh4eb" if BR2_sh4eb - default "sh4a" if BR2_sh4a - default "sh4aeb" if BR2_sh4aeb - default "sh64" if BR2_sh64 - default "sparc" if BR2_sparc - - -config BR2_ENDIAN - string - default "LITTLE" if BR2_arm || BR2_bfin || BR2_i386 || BR2_mipsel || BR2_mips64el || \ - BR2_sh3 || BR2_sh4 || BR2_sh4a || BR2_x86_64 || BR2_sh64 || \ - BR2_microblazeel - default "BIG" if BR2_armeb || BR2_avr32 || BR2_m68k || BR2_mips || BR2_mips64 || \ - BR2_powerpc || BR2_sh2 || BR2_sh2a || \ - BR2_sh3eb || BR2_sh4eb || BR2_sh4aeb || BR2_sparc || \ - BR2_microblazebe - -config BR2_GCC_TARGET_TUNE - string - default i386 if BR2_x86_i386 - default i486 if BR2_x86_i486 - default i586 if BR2_x86_i586 - default pentium-mmx if BR2_x86_pentium_mmx - default i686 if BR2_x86_i686 - default pentiumpro if BR2_x86_pentiumpro - default pentium-m if BR2_x86_pentium_m - default pentium2 if BR2_x86_pentium2 - default pentium3 if BR2_x86_pentium3 - default pentium4 if BR2_x86_pentium4 - default prescott if BR2_x86_prescott - default nocona if BR2_x86_nocona - default core2 if BR2_x86_core2 - default atom if BR2_x86_atom - default k8 if BR2_x86_opteron - default k8-sse3 if BR2_x86_opteron_sse3 - default barcelona if BR2_x86_barcelona - default k6 if BR2_x86_k6 - default k6-2 if BR2_x86_k6_2 - default athlon if BR2_x86_athlon - default athlon-4 if BR2_x86_athlon_4 - default winchip-c6 if BR2_x86_winchip_c6 - default winchip2 if BR2_x86_winchip2 - default c3 if BR2_x86_c3 - default c3-2 if BR2_x86_c32 - default geode if BR2_x86_geode - default generic if BR2_x86_generic - default arm600 if BR2_arm600 - default arm610 if BR2_arm610 - default arm620 if BR2_arm620 - default arm7tdmi if BR2_arm7tdmi - default arm7tdmi if BR2_arm720t - default arm7tdmi if BR2_arm740t - default arm920 if BR2_arm920 - default arm920t if BR2_arm920t - default arm922t if BR2_arm922t - default arm926ej-s if BR2_arm926t - default arm1136j-s if BR2_arm1136j_s - default arm1136jf-s if BR2_arm1136jf_s - default arm1176jz-s if BR2_arm1176jz_s - default arm1176jzf-s if BR2_arm1176jzf_s - default cortex-a8 if BR2_cortex_a8 - default cortex-a9 if BR2_cortex_a9 - default strongarm110 if BR2_sa110 - default strongarm1100 if BR2_sa1100 - default xscale if BR2_xscale - default iwmmxt if BR2_iwmmxt - default 68000 if BR2_m68k_68000 - default 68010 if BR2_m68k_68010 - default 68020 if BR2_m68k_68020 - default 68030 if BR2_m68k_68030 - default 68040 if BR2_m68k_68040 - default 68060 if BR2_m68k_68060 - default mips1 if BR2_mips_1 - default mips2 if BR2_mips_2 - default mips3 if BR2_mips_3 - default mips4 if BR2_mips_4 - default mips32 if BR2_mips_32 - default mips32r2 if BR2_mips_32r2 - default mips64 if BR2_mips_64 - default mips64r2 if BR2_mips_64r2 - default 401 if BR2_powerpc_401 - default 403 if BR2_powerpc_403 - default 405 if BR2_powerpc_405 - default 405fp if BR2_powerpc_405fp - default 440 if BR2_powerpc_440 - default 440fp if BR2_powerpc_440fp - default 505 if BR2_powerpc_505 - default 601 if BR2_powerpc_601 - default 602 if BR2_powerpc_602 - default 603 if BR2_powerpc_603 - default 603e if BR2_powerpc_603e - default 604 if BR2_powerpc_604 - default 604e if BR2_powerpc_604e - default 620 if BR2_powerpc_620 - default 630 if BR2_powerpc_630 - default 740 if BR2_powerpc_740 - default 7400 if BR2_powerpc_7400 - default 7450 if BR2_powerpc_7450 - default 750 if BR2_powerpc_750 - default 801 if BR2_powerpc_801 - default 821 if BR2_powerpc_821 - default 823 if BR2_powerpc_823 - default 860 if BR2_powerpc_860 - default 970 if BR2_powerpc_970 - default 8540 if BR2_powerpc_8540 - default 8548 if BR2_powerpc_8548 - default e300c2 if BR2_powerpc_e300c2 - default e300c3 if BR2_powerpc_e300c3 - default e500mc if BR2_powerpc_e500mc - default v7 if BR2_sparc_v7 - default cypress if BR2_sparc_cypress - default v8 if BR2_sparc_v8 - default supersparc if BR2_sparc_supersparc - default hypersparc if BR2_sparc_hypersparc - default sparclite if BR2_sparc_sparclite - default f930 if BR2_sparc_f930 - default f934 if BR2_sparc_f934 - default sparclite86x if BR2_sparc_sparclite86x - default sparclet if BR2_sparc_sparclet - default tsc701 if BR2_sparc_tsc701 - default v9 if BR2_sparc_v9 - default v9 if BR2_sparc_v9a - default v9 if BR2_sparc_v9b - default ultrasparc if BR2_sparc_ultrasparc - default ultrasparc3 if BR2_sparc_ultrasparc3 - default niagara if BR2_sparc_niagara - -config BR2_GCC_TARGET_ARCH - string - default i386 if BR2_x86_i386 - default i486 if BR2_x86_i486 - default i586 if BR2_x86_i586 - default pentium-mmx if BR2_x86_pentium_mmx - default i686 if BR2_x86_i686 - default pentiumpro if BR2_x86_pentiumpro - default pentium-m if BR2_x86_pentium_m - default pentium2 if BR2_x86_pentium2 - default pentium3 if BR2_x86_pentium3 - default pentium4 if BR2_x86_pentium4 - default prescott if BR2_x86_prescott - default nocona if BR2_x86_nocona - default core2 if BR2_x86_core2 - default atom if BR2_x86_atom - default k8 if BR2_x86_opteron - default k8-sse3 if BR2_x86_opteron_sse3 - default barcelona if BR2_x86_barcelona - default k6 if BR2_x86_k6 - default k6-2 if BR2_x86_k6_2 - default athlon if BR2_x86_athlon - default athlon-4 if BR2_x86_athlon_4 - default winchip-c6 if BR2_x86_winchip_c6 - default winchip2 if BR2_x86_winchip2 - default c3 if BR2_x86_c3 - default c3-2 if BR2_x86_c32 - default geode if BR2_x86_geode - default armv4t if BR2_arm7tdmi - default armv3 if BR2_arm610 - default armv3 if BR2_arm710 - default armv4t if BR2_arm720t - default armv4t if BR2_arm920t - default armv4t if BR2_arm922t - default armv5te if BR2_arm926t - default armv5t if BR2_arm10t - default armv6j if BR2_arm1136jf_s - default armv6zk if BR2_arm1176jz_s - default armv6zk if BR2_arm1176jzf_s - default armv7-a if BR2_cortex_a8 - default armv7-a if BR2_cortex_a9 - default armv4 if BR2_sa110 - default armv4 if BR2_sa1100 - default armv5te if BR2_xscale - default iwmmxt if BR2_iwmmxt - default 68000 if BR2_m68k_68000 - default 68010 if BR2_m68k_68010 - default 68020 if BR2_m68k_68020 - default 68030 if BR2_m68k_68030 - default 68040 if BR2_m68k_68040 - default 68060 if BR2_m68k_68060 - -config BR2_GCC_TARGET_ABI - string - default apcs-gnu if BR2_ARM_OABI - default aapcs-linux if BR2_ARM_EABI - default 32 if BR2_MIPS_OABI32 - default n32 if BR2_MIPS_NABI32 - default 64 if BR2_MIPS_NABI64 - default altivec if BR2_powerpc && BR2_PPC_ABI_altivec - default no-altivec if BR2_powerpc && BR2_PPC_ABI_no-altivec - default spe if BR2_powerpc && BR2_PPC_ABI_spe - default no-spe if BR2_powerpc && BR2_PPC_ABI_no-spe - default ibmlongdouble if BR2_powerpc && BR2_PPC_ABI_ibmlongdouble - default ieeelongdouble if BR2_powerpc && BR2_PPC_ABI_ieeelongdouble - -config BR2_GCC_TARGET_CPU - string - default sparchfleon if BR2_sparc_sparchfleon - default sparchfleonv8 if BR2_sparc_sparchfleonv8 - default sparcsfleon if BR2_sparc_sparcsfleon - default sparcsfleonv8 if BR2_sparc_sparcsfleonv8 -- cgit v1.2.3