From 58a4d81047891bf2bcfaa141f81b4ea34f0c3594 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Wed, 9 Oct 2013 00:30:58 -0400 Subject: fix up minor xula2 typos --- hdl/main_xula2.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hdl') diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v index 49581e1..4436665 100644 --- a/hdl/main_xula2.v +++ b/hdl/main_xula2.v @@ -36,7 +36,7 @@ module main ( wire [7:0] rx_byte; wire [7:0] tx_byte; wire uart_flag; - simple_uart ( + simple_uart #( .CLOCK_DIVIDE(313) // for 12MHz clock ) simple_uart_inst ( .clk(clock_12mhz), -- cgit v1.2.3