From 0754c0f771c51d48107c5c96d79a512ce56cce0a Mon Sep 17 00:00:00 2001 From: Andrew J Meyer Date: Wed, 6 Mar 2013 18:47:43 -0500 Subject: added the base files --- hdl/project.v | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 hdl/project.v (limited to 'hdl') diff --git a/hdl/project.v b/hdl/project.v new file mode 100644 index 0000000..753597b --- /dev/null +++ b/hdl/project.v @@ -0,0 +1,26 @@ +module project + ( + output wire LED_output_0, + output wire LED_output_1, + output wire LED_output_2, + output wire LED_output_3, + output wire LED_output_4, + output wire LED_output_5, + output wire LED_output_6, + input wire Switch_input_0, + input wire Switch_input_1, + input wire Switch_input_2, + input wire Switch_input_3, + input wire SYSTEMCLOCK, + input wire PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low- + ); + + assign LED_output_0 = 1'b0; + assign LED_output_1 = 1'b0; + assign LED_output_2 = 1'b0; + assign LED_output_3 = 1'b0; + assign LED_output_4 = 1'b0; + assign LED_output_5 = 1'b0; + assign LED_output_6 = 1'b0; + +endmodule \ No newline at end of file -- cgit v1.2.3