From 40affb5169e1d30f25a0906acb56f2cbbb74b51f Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 8 Oct 2013 23:48:29 -0400 Subject: basic rot13 UART demo working --- hdl/main_xula2.v | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'hdl/main_xula2.v') diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v index 926f634..2f0d662 100644 --- a/hdl/main_xula2.v +++ b/hdl/main_xula2.v @@ -32,6 +32,30 @@ module main ( reg throb_led = 0; assign chan[10] = throb_led; + wire [7:0] rx_byte; + wire [7:0] tx_byte; + wire uart_flag; + simple_uart simple_uart_inst ( + .clk(clock_12mhz), + .rst(reset), + .rx(chan[17]), + .tx(chan[18]), + .transmit(uart_flag), + .tx_byte(tx_byte), + .received(uart_flag), + .rx_byte(rx_byte), + .is_receiving(), + .is_transmitting(), + .recv_error() + ); + + rot13 rot13_inst ( + .clock(clock_12mhz), + .reset(reset), + .in_char(rx_byte), + .out_char(tx_byte) + ); + always @(posedge clock_12mhz) begin if (reset) begin throb_counter <= 0; -- cgit v1.2.3