From 03e710c5a2e75b889550f06852e87c2f869ea152 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 12 Nov 2013 18:25:21 -0500
Subject: fix typos revealed by going through QUICK_START

---
 README | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'README')

diff --git a/README b/README
index e303770..ff2aad0 100644
--- a/README
+++ b/README
@@ -1,5 +1,5 @@
 
-* * < DELTEME > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+* * * DELETE ME * * * * * * * DELETE ME * * * * * * * DELETE ME * * * * * * * *
 
 This folder contains a template Verilog/VHDL HDL project with a basic build
 system for using the Xilinx ISE toolchain to target FPGAs.                  
@@ -10,11 +10,15 @@ minimum you will need to copy ./contrib/Makefile.example to ./Makefile.
                                                                             
 Hint: search this file for "<board>"                                        
 
-* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ ^
 
 == About =====================================================================
 
-<fill this part in>
+
+
+  <<<<fill this part in>>>>
+
+
 
 See COPYING for copyright and licensing information.
 
-- 
cgit v1.2.3