From eef34f2975ddb40d0aaedd7a0182111c22db47cf Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Thu, 14 Mar 2013 13:11:23 -0400
Subject: 'main', not 'project' top module by default

---
 Makefile      | 2 +-
 hdl/project.v | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 0fd1347..3b12d98 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 project = project
-top_module = project
+top_module = main
 vendor = xilinx
 
 # This is the chipset from the Xilinx SP605 dev board
diff --git a/hdl/project.v b/hdl/project.v
index 753597b..9e382a5 100644
--- a/hdl/project.v
+++ b/hdl/project.v
@@ -1,4 +1,4 @@
-module project
+module main
    (
     output wire LED_output_0,
     output wire LED_output_1,
@@ -23,4 +23,4 @@ module project
    assign LED_output_5 = 1'b0;
    assign LED_output_6 = 1'b0;
 
-endmodule
\ No newline at end of file
+endmodule
-- 
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