From b31c07157b7b8ca7e8823749e140fcab24b787d2 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 8 Oct 2013 22:05:21 -0400 Subject: working xula2 sim/syn/prog system --- Makefile | 33 +++++++++++++------------- README.xula2 | 16 +++++++++++++ contrib/xilinx.mk | 4 ++-- contrib/xula2.mk | 9 +++++++ hdl/main_xula2.v | 62 ++++++++++++++++++++++++++++++++++++++++++++++++ hdl/main_xula2.vhd | 33 ++++++++++++++++++++++++++ tb/xula2_tb.v | 43 ++++++++++++++++++++++++++++++++++ tb/xula2_tb.wcfg | 30 ++++++++++++++++++++++++ xula2.bitconf | 7 ++++++ xula2.bmm | 1 + xula2.ucf | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 11 files changed, 289 insertions(+), 18 deletions(-) create mode 100644 README.xula2 create mode 100644 contrib/xula2.mk create mode 100644 hdl/main_xula2.v create mode 100644 hdl/main_xula2.vhd create mode 100755 tb/xula2_tb.v create mode 100644 tb/xula2_tb.wcfg create mode 100644 xula2.bitconf create mode 100644 xula2.bmm create mode 100644 xula2.ucf diff --git a/Makefile b/Makefile index eaa646e..e89469b 100644 --- a/Makefile +++ b/Makefile @@ -5,18 +5,18 @@ top_module := main vendor := xilinx # This is the chipset from the Xilinx SP605 dev board -board := sp605 -family := spartan6 -device := xc6slx45t -speedgrade := -3 -device_package := fgg484 +#board := sp605 +#family := spartan6 +#device := xc6slx45t +#speedgrade := -3 +#device_package := fgg484 # This is the chipset for the Xess Xula 2 dev board -#board := xula2 -#family := spartan6 -#device := XC6SLX25 -#speedgrade := -2 -#device_package := ft256 +board := xula2 +family := spartan6 +device := XC6SLX25 +speedgrade := -2 +device_package := ftg256 part := $(device)$(speedgrade)-$(device_package) @@ -26,16 +26,16 @@ iseenv := /opt/Xilinx/14.3/ISE_DS/ # list all .v files explicitly with verilog_files (no hdl/*.v business) verilog_files := hdl/$(top_module)_$(board).v +verilog_files += hdl/rot13.v #verilog_files += hdl/yours.v -tbfiles := tb/main_tb.v -tbfiles += tb/another_tb.v -tbfiles += tb/trivial_test.v -tbfiles += tb/complicated_test.v +tbfiles := tb/rot13_tb.v +tbfiles += tb/xula2_tb.v +#tbfiles += tb/sp605_tb.v # what gets run alltests := test/trivial_test -alltests += test/complicated_test +alltests += test/rot13_tb # list of .xco files, eg "cores/bram.xco". do not include DCM files. xilinx_cores := @@ -48,4 +48,5 @@ mcs_datawidth := 16 include ./contrib/xilinx.mk # Example hardware-specific targets (eg, upload via SPI) -include ./contrib/example-device.mk +#include ./contrib/example-device.mk +include ./contrib/xula2.mk diff --git a/README.xula2 b/README.xula2 new file mode 100644 index 0000000..3ca7d50 --- /dev/null +++ b/README.xula2 @@ -0,0 +1,16 @@ + +To upload bitfiles to the xula2 board, you first need to install the "xstools" +python package: + + https://pypi.python.org/pypi/XsTools/ + +IMPORTANT: if you get the following error when using the xstest.py python tool +with a xula2 board on linux: + + usb.core.USBError: [Errno 5] Input/output error + +and then your board resets (LED turns off), then you probably need to first +upgrade the PIC microcontroller firmware: + + sudo xsusbprg.py + diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index 458d73e..aae76a2 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -129,9 +129,9 @@ programming_files: build/$(project).bit build/$(project).mcs build/$(project).mcs: build/$(project).bit @bash -c "$(xil_env); promgen -w -data_width $(mcs_datawidth) -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit" -build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr +build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr $(board).bitconf @bash -c "$(xil_env); \ - bitgen $(intstyle) -g Binary:yes -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit" + bitgen $(intstyle) -f ../$(board).bitconf -w $(project)_par.ncd $(project).bit" build/$(project)_par.ncd: build/$(project).ncd build/$(project)_post_map.twr diff --git a/contrib/xula2.mk b/contrib/xula2.mk new file mode 100644 index 0000000..9c06b3b --- /dev/null +++ b/contrib/xula2.mk @@ -0,0 +1,9 @@ +# xula2 device-specific make targets + +.PHONY: prog + +prog: build/$(project).bit + @xsload.py --fpga build/$(project).bit + +prog_flash: build/$(project).bit + @xsload.py --flash build/$(project).bit diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v new file mode 100644 index 0000000..926f634 --- /dev/null +++ b/hdl/main_xula2.v @@ -0,0 +1,62 @@ +/* + * main_xula2.v + * + * Copyright: (C) 2013 LeafLabs, LLC + * License: MIT License (See LICENSE file) + * Author: Bryan Newbold + * Date: October 2013 + * + * This is the top-level module for the Xess Corp Xula 2 development board. + * + * TODO if using this as a template for another design: + * - use a clock buffer, even if sticking with 12mhz + */ + +module main ( + input wire clock_12mhz, + inout wire [31:0] chan, + inout wire chan_clk, + + //// Flash and microSD I/O + output wire microsd_cs, + output wire flash_cs, + output wire flash_sclk, + output wire flash_mosi, + output wire flash_miso + ); + + wire reset; + assign reset = chan[0]; + + reg [22:0] throb_counter = 0; + reg throb_led = 0; + assign chan[10] = throb_led; + + always @(posedge clock_12mhz) begin + if (reset) begin + throb_counter <= 0; + throb_led <= 0; + end else begin + if (throb_counter >= 23'd06_000_000) begin + throb_led <= !throb_led; + throb_counter <= 23'd0; + end else begin + throb_counter <= throb_counter + 23'd1; + end + end + end + + // Tie off unused outputs + assign microsd_cs = 1'bZ; + assign flash_cs = 1'bZ; + assign flash_sclk = 1'bZ; + assign flash_mosi = 1'bZ; + assign flash_miso = 1'bZ; + assign chan[31] = 1'bz; +/* + assign chan[31:21] = 11'bZ; + assign chan[19:1] = 19'bZ; + assign chan_clk = 1'bZ; +*/ + +endmodule diff --git a/hdl/main_xula2.vhd b/hdl/main_xula2.vhd new file mode 100644 index 0000000..57368f8 --- /dev/null +++ b/hdl/main_xula2.vhd @@ -0,0 +1,33 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity blinker is + Port ( clk_i : in STD_LOGIC; + blinker_o : out STD_LOGIC); +end blinker; + +architecture Behavioral of blinker is +signal cnt_r : std_logic_vector(22 downto 0) := (others=>'0'); +begin + +process(clk_i) is +begin + if rising_edge(clk_i) then + cnt_r <= cnt_r + 1; + end if; +end process; + +blinker_o <= cnt_r(22); + +end Behavioral; diff --git a/tb/xula2_tb.v b/tb/xula2_tb.v new file mode 100755 index 0000000..6fd8316 --- /dev/null +++ b/tb/xula2_tb.v @@ -0,0 +1,43 @@ +`timescale 1ns/1ps +module xula2_tb; + +reg synth_clk_12mhz; +always @(synth_clk_12mhz) begin + #83333.33 synth_clk_12mhz <= ~synth_clk_12mhz; +end + +initial begin + // the first event that sets the clock in motion + #0 synth_clk_12mhz <= 1'b0; +end + +reg reset; +wire led; +wire [31:0] chan; +assign chan[0] = reset; +assign led = chan[10]; + +main main_inst ( + .clock_12mhz(synth_clk_12mhz), + .chan(chan), + .chan_clk(), + .microsd_cs(), + .flash_cs(), + .flash_sclk(), + .flash_mosi(), + .flash_miso() +); + + +initial begin + #0 + reset <= 1'b1; + #1000000000 // 1 s delay + #1000000000 // 1 s delay + #1000000000 // 1 s delay + reset <= 1'b0; + + $finish(); +end + +endmodule diff --git a/tb/xula2_tb.wcfg b/tb/xula2_tb.wcfg new file mode 100644 index 0000000..7a75798 --- /dev/null +++ b/tb/xula2_tb.wcfg @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + synth_clk_12mhz + synth_clk_12mhz + + + chan[31:0] + chan[31:0] + + + reset + reset + + + led + led + + diff --git a/xula2.bitconf b/xula2.bitconf new file mode 100644 index 0000000..599289d --- /dev/null +++ b/xula2.bitconf @@ -0,0 +1,7 @@ +-g Binary:yes +# below are xula2-specific configurations +-g UnusedPin:Pullnone +-g TckPin:Pullnone +#-g StartupClk:JtagClk # for JTAG upload +-g StartupClk:Cclk # for serial flash +-g ConfigRate:10 # for fast serial flashing diff --git a/xula2.bmm b/xula2.bmm new file mode 100644 index 0000000..c915ec8 --- /dev/null +++ b/xula2.bmm @@ -0,0 +1 @@ +// Empty file; this is a "Block Ram Memory Map" diff --git a/xula2.ucf b/xula2.ucf new file mode 100644 index 0000000..ae04f81 --- /dev/null +++ b/xula2.ucf @@ -0,0 +1,69 @@ +# ============================================================================ +# Xess Corp XuLa 2 +# ============================================================================ + +# Originally written October 2013 by LeafLabs, LLC (leaflabs.com). + +# The .ucf supplied by Xess is under GPL. +# https://raw.github.com/xesscorp/XuLA2/master/FPGA/XuLA_lib/XuLA2.ucf + +# This file was written from scratch from the manual. It is intended to be +# reused and copy/pasted from with no copyright or attribution necessary. In +# that an explicit license is necessary for such a file, it is Creative Commons +# Zero. + +# ==== Clocks ==== + +NET "clock_12mhz" LOC = "A9"; +NET "clock_12mhz" IOSTANDARD = LVTTL; +NET "clock_12mhz" TNM_NET = "clock_12mhz"; +TIMESPEC "TS_clock_12mhz" = PERIOD "clock_12mhz" 12 MHz HIGH 50%; + +# ==== Prototyping Header (GPIO) ==== + +NET "chan_clk" LOC = "T7" | IOSTANDARD = LVTTL ; + +NET "chan<0>" LOC = "R7" | IOSTANDARD = LVTTL ; +NET "chan<1>" LOC = "R15" | IOSTANDARD = LVTTL ; +NET "chan<2>" LOC = "R16" | IOSTANDARD = LVTTL ; +NET "chan<3>" LOC = "M15" | IOSTANDARD = LVTTL ; +NET "chan<4>" LOC = "M16" | IOSTANDARD = LVTTL ; +NET "chan<5>" LOC = "K15" | IOSTANDARD = LVTTL ; +NET "chan<6>" LOC = "K16" | IOSTANDARD = LVTTL ; +NET "chan<7>" LOC = "J16" | IOSTANDARD = LVTTL ; +NET "chan<8>" LOC = "J14" | IOSTANDARD = LVTTL ; +NET "chan<9>" LOC = "F15" | IOSTANDARD = LVTTL ; +NET "chan<10>" LOC = "F16" | IOSTANDARD = LVTTL ; +NET "chan<11>" LOC = "C16" | IOSTANDARD = LVTTL ; +NET "chan<12>" LOC = "C15" | IOSTANDARD = LVTTL ; +NET "chan<13>" LOC = "B16" | IOSTANDARD = LVTTL ; +NET "chan<14>" LOC = "B15" | IOSTANDARD = LVTTL ; +NET "chan<15>" LOC = "T4" | IOSTANDARD = LVTTL ; +NET "chan<16>" LOC = "R2" | IOSTANDARD = LVTTL ; +NET "chan<17>" LOC = "R1" | IOSTANDARD = LVTTL ; +NET "chan<18>" LOC = "M2" | IOSTANDARD = LVTTL ; +NET "chan<19>" LOC = "M1" | IOSTANDARD = LVTTL ; +NET "chan<20>" LOC = "K3" | IOSTANDARD = LVTTL ; +NET "chan<21>" LOC = "J4" | IOSTANDARD = LVTTL ; +NET "chan<22>" LOC = "H1" | IOSTANDARD = LVTTL ; +NET "chan<23>" LOC = "H2" | IOSTANDARD = LVTTL ; +NET "chan<24>" LOC = "F1" | IOSTANDARD = LVTTL ; +NET "chan<25>" LOC = "F2" | IOSTANDARD = LVTTL ; +NET "chan<26>" LOC = "E1" | IOSTANDARD = LVTTL ; +NET "chan<27>" LOC = "E2" | IOSTANDARD = LVTTL ; +NET "chan<28>" LOC = "C1" | IOSTANDARD = LVTTL ; +NET "chan<29>" LOC = "B1" | IOSTANDARD = LVTTL ; +NET "chan<30>" LOC = "B2" | IOSTANDARD = LVTTL ; +NET "chan<31>" LOC = "A2" | IOSTANDARD = LVTTL ; + +# ==== SDRAM ==== +# TODO + +# ==== SPI Flash and uSD Card ==== + +NET "microsd_cs" LOC = "T8" | IOSTANDARD = LVTTL ; +NET "flash_cs" LOC = "T3" | IOSTANDARD = LVTTL ; +NET "flash_sclk" LOC = "R11" | IOSTANDARD = LVTTL ; +NET "flash_mosi" LOC = "T10" | IOSTANDARD = LVTTL ; +NET "flash_miso" LOC = "P10" | IOSTANDARD = LVTTL ; + -- cgit v1.2.3