From 8e55b5eee512c3088ff01719875249640cf1efca Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 12 Nov 2013 20:04:08 -0500
Subject: add a "complicated" Makefile for testing

Also the corresponding top-level module (for Xula2)
---
 contrib/Makefile.complicated | 42 ++++++++++++++++++++++++++
 hdl/complicated.v            | 71 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 contrib/Makefile.complicated
 create mode 100644 hdl/complicated.v

diff --git a/contrib/Makefile.complicated b/contrib/Makefile.complicated
new file mode 100644
index 0000000..883248a
--- /dev/null
+++ b/contrib/Makefile.complicated
@@ -0,0 +1,42 @@
+# This makefile is helpful for build system development because it exersizes
+# more features (eg, coregen stuff).
+# You may wish to symlink it from the top-level Makefile
+
+project := complicatedproj
+top_module := complicated
+vendor := xilinx
+
+include ./contrib/xula2/settings.mk
+extra_includes += ./contrib/xula2/targets.mk
+
+part := $(device)$(speedgrade)-$(device_package)
+
+hostbits := 64
+
+iseenv := /opt/Xilinx/14.3/ISE_DS/
+#iseenv := /opt/Xilinx/14.7/ISE_DS/
+
+verilog_files += hdl/complicated.v
+verilog_files += hdl/rot13.v
+
+vhdl_files +=
+
+extra_prj +=
+
+tbfiles += tb/rot13_tb.v
+
+gitcommit = $(shell (git log --abbrev=8 --oneline -n 1 2> /dev/null || echo "00000000") | head -c 8)
+build_unixtime = $(shell date +%s || echo "0")
+vgenerics += "GIT_COMMIT=h$(gitcommit)"
+vgenerics += "BUILD_UNIX_TIME=d$(build_unixtime)"
+
+xilinx_cores += cores/bram.xco
+
+mcs_datawidth := 32
+
+bmm_file := contrib/empty.bmm
+
+include ./contrib/xilinx.mk
+
+include $(extra_includes)
+
diff --git a/hdl/complicated.v b/hdl/complicated.v
new file mode 100644
index 0000000..4d31588
--- /dev/null
+++ b/hdl/complicated.v
@@ -0,0 +1,71 @@
+/*
+ * complicated.v
+ *
+ * Copyright: (C) 2013 LeafLabs, LLC
+ * License: MIT License (See LICENSE file)
+ * Author: Bryan Newbold <bnewbold@leaflabs.com>
+ * Date: November 2013
+ *
+ * This is an intentionally complicated top-level file.
+ *
+ * TODO if using this as a template for another design:
+ *  - use a clock buffer, even if sticking with 12mhz
+ */
+
+module complicated (
+    input wire clock_12mhz,
+    inout wire [31:0] chan,
+    inout wire chan_clk,
+
+    //// Flash and microSD I/O
+    output wire microsd_cs,
+    output wire flash_cs,
+    output wire flash_sclk,
+    output wire flash_mosi,
+    output wire flash_miso
+    );
+
+    parameter GIT_COMMIT = 0;
+    parameter BUILD_UNIX_TIME = 0;
+
+    wire reset = chan[0];
+
+    reg [22:0] throb_counter = 0;
+    reg throb_led = 0;
+    assign chan[10] = throb_led;
+
+    bram bram_inst (
+        .clka(clock_12mhz),
+        .ena(1'b0),
+        .wea(1'b1),
+        .addra(10),
+        .dina(11),
+        .clkb(clock_12mhz),
+        .rstb(reset),
+        .enb(1'b0),
+        .addrb(13),
+        .doutb()
+        );
+
+    always @(posedge clock_12mhz) begin
+        if (reset) begin
+            throb_counter <= 0;
+            throb_led <= 0;
+        end else begin
+            if (throb_counter >= 23'd06_000_000) begin
+                throb_led <= !throb_led;
+                throb_counter <= 23'd0;
+            end else begin
+                throb_counter <= throb_counter + 23'd1;
+            end
+        end
+    end
+
+    // Tie off unused outputs
+    assign microsd_cs = 1'bZ;
+    assign flash_cs = 1'bZ;
+    assign flash_sclk = 1'bZ;
+    assign flash_mosi = 1'bZ;
+    assign flash_miso = 1'bZ;
+
+endmodule
-- 
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