From 078932696fc9f8ec97e6efddea3019f4cb0669a9 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Wed, 9 Oct 2013 00:31:49 -0400
Subject: commit TODO list

---
 TODO.template | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 TODO.template

diff --git a/TODO.template b/TODO.template
new file mode 100644
index 0000000..6b51e83
--- /dev/null
+++ b/TODO.template
@@ -0,0 +1,18 @@
+
+switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)?
+    or is that too gmake specific...
+
+BUG: synth still seems to continue even if first build (verilog compile)
+     fails
+
+add .PRECIOUS for intermediate files we don't want to get deleted
+
+for fpga_editor:
+    DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file>
+
+effort levels seem high by default:
+    Overall effort level (-ol):   High 
+    Router effort level (-rl):    High 
+
+impact:
+    impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing)
-- 
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