diff options
Diffstat (limited to 'project.xise')
| -rw-r--r-- | project.xise | 30 |
1 files changed, 10 insertions, 20 deletions
diff --git a/project.xise b/project.xise index cff885d..42b5b99 100644 --- a/project.xise +++ b/project.xise @@ -14,18 +14,7 @@ <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/> - <files> - <file xil_pn:name="hdl/project.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> - </file> - <file xil_pn:name="project.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> - <file xil_pn:name="project.bmm" xil_pn:type="FILE_BMM"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> - </files> + <files/> <properties> <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> @@ -88,6 +77,7 @@ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> @@ -140,9 +130,9 @@ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Module|project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="../hdl/project.v" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> @@ -205,11 +195,11 @@ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> @@ -219,10 +209,10 @@ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> - <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="_map.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="_timesim.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="_synthesis.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="_translate.v" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |